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9.2.5 Register Description .................................................................................................. 104
9.3 Frame Buffer....................................................................................................... 105
9.3.1 Data Management ..................................................................................................... 105
9.3.2 User accessible Frame Content ................................................................................ 106
9.3.3 Interrupt Handling ...................................................................................................... 106
9.4 Voltage Regulators (AVREG, DVREG) .............................................................. 108
9.4.1 Overview ................................................................................................................... 108
9.4.2 Configuration ............................................................................................................. 108
9.4.3 Data Interpretation ..................................................................................................... 108
9.4.4 Register Description .................................................................................................. 109
9.5 Battery Monitor (BATMON) ................................................................................ 111
9.5.1 Overview ................................................................................................................... 111
9.5.2 Configuration ............................................................................................................. 111
9.5.3 Data Interpretation ..................................................................................................... 111
9.5.4 Interrupt Handling ...................................................................................................... 112
9.5.5 Register Description .................................................................................................. 112
9.6 Crystal Oscillator (XOSC) ................................................................................... 114
9.6.1 Overview ................................................................................................................... 114
9.6.2 Integrated Oscillator Setup ........................................................................................ 114
9.6.3 External Reference Frequency Setup ....................................................................... 115
9.6.4 Master Clock Signal Output (CLKM).......................................................................... 115
9.6.5 Register Description .................................................................................................. 116
9.7 Frequency Synthesizer (PLL) ............................................................................. 118
9.7.1 Overview ................................................................................................................... 118
9.7.2 RF Channel Selection................................................................................................ 118
9.7.3 Frequency Agility ....................................................................................................... 118
9.7.4 Calibration Loops ...................................................................................................... 118
9.7.5 Interrupt Handling ...................................................................................................... 119
9.7.6 Register Description .................................................................................................. 119
9.8 Automatic Filter Tuning (FTN) ............................................................................ 122
9.8.1 Overview ................................................................................................................... 122
9.8.2 Register Description .................................................................................................. 122
10 Radio Transceiver Usage ............................................................. 123
10.1 Frame Receive Procedure ............................................................................... 123
10.2 Frame Transmit Procedure .............................................................................. 124
11 AT86RF232 Extended Feature Set ............................................... 125
11.1 Security Module (AES) ..................................................................................... 125
11.1.1 Overview ................................................................................................................. 125
11.1.2 Security Module Preparation ................................................................................... 125
11.1.3 Security Key Setup .................................................................................................. 126
11.1.4 Security Operation Modes ....................................................................................... 126
11.1.5 Data Transfer – Fast SRAM Access ........................................................................ 129
11.1.6 Start of Security Operation and Status .................................................................... 130
11.1.7 SRAM Register Summary ....................................................................................... 130
11.1.8 AES SRAM Configuration Register ......................................................................... 130
11.2 Random Number Generator ............................................................................. 133
11.2.1 Overview ................................................................................................................. 133
11.2.2 Register Description ................................................................................................ 133
172
AT86RF232
8321A – MCU Wireless – 10/11
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